PC-bounded diodes are one of the major ESD devices for planar CMOS technology due to their particular advantages for use with ESDs. For example, PC-bounded diodes have low on-state resistance (Ron) and high failure current for devices similar in size. In addition, PC-bounded diodes have low voltage overshoot, which is another desired quality for ESD applications. FIG. 1 depicts a conventional PC-bounded diode that may be used, for example, with both 20 nm and 28 nm planar CMOS technology nodes. As illustrated, the diode is formed between shallow trench isolation (STI) regions 101 in NWell 103 in a P-type substrate 105. On one side, a cathode 107 is formed over N+ region 109, on the other side, an anode 111 is formed over P+ region 113, and in between the cathode and the anode, a gate 115 is formed, electrically connected to the anode. A direct current flow from the anode to the cathode is shown by arrows 117, and the gate length is indicated by arrow 119.
Adverting to FIG. 2, a layout of a conventional PC-bounded diode that may be used in 20 nm CMOS technology is depicted. As illustrated, a gate structure 201, including multiple contacts 203, is formed over an active region 205, for example, a source/drain region. The active region 205 is formed over an NWell 207, which is formed over a substrate 209.
Although conventional PC-bounded diodes are commonly used for 20 nm and 28 nm planar CMOS technology nodes, at smaller technology nodes, such as 14 nm technology nodes, FINFETs are preferably used due to their superior immunity to short-channel effects. In such devices, the depletion-layout width is limited to within the fin width.
Contrary to conventional PC-bounded diodes used for planar CMOS technology nodes, FINFETs are non-planar transistors built on a substrate, for example, silicon on insulator (SOI) substrate or bulk substrate. FINFETs are typically used to construct PC-bounded diodes with similar methods as those utilized in planar technology and with the cathodes and anodes of a particular PC-bounded diode being doped in the same manner. Using such similar methods as those utilized in planar technology, a source terminal includes a well (i.e., no junction), and a drain-well junction serves as an ESD diode junction. However, under this approach, both design and process issues arise because the resulting junction area of the FINFET is too small. The junction area of a conventional PC-bounded diode can be calculated as the fin width times the fin height (i.e., junction area=fin height×fin width). A limiting factor with this approach is that in order to provide a high ESD protection capability, a large number of FINFETs must be connected in parallel, which thereby results in a reduced efficiency of the PC-bounded diode's layout (i.e., reduction in area efficiency).
A need therefore exists for methodology enabling the formation of ESD diodes that are compatible with FINFET process flow while having a large enough junction area to reduce the discharge ESD current density, and the resulting device.